Python Forum

I need a library that can generate an image with the following diagram type:

Each block has
- a name
- some input (labeled) pins
- some output (labeled) pins
The connections are between output pin of one block and input pin of another block.
The library should also automatically computes the position of blocks.

I'm not sure if you will be able to use this for your application, but it's worth looking into
https://pypi.org/project/graphviz/
github: https://github.com/xflr6/graphviz

The reason I think it might work is that I found another application built on top of graphviz, which generates a UML model, closer to what you're trying to do. That pachage is located here: https://pypi.org/project/pg-diagram/

Thank you for your answer.
Graphviz seems to be similar to networkx library, but I think it generates better diagrams. There is the concept of ports that can be useful for me. The problem is that also in graphviz the connection (the edge) has a single label. In the pg_diagram the label of the ports seems to be inside of the block itself. Probably is the only possibile solution if I want to use existing libraries.

I haven't actually played with Graphviz, but I have an application that I'm working on now where it might fit nicely. I'll play around with it for a few days and get back with whatever I've garnered.

For 2 labels look at https://stackoverflow.com/q/20149082/4046632

(Nov-13-2020, 03:30 AM)buran Wrote: [ -> ]For 2 labels look at https://stackoverflow.com/q/20149082/4046632

Yes, headlabel and taillabel are the attributes I was looking for
Unfortunately they overlap in the automatic visualization. Now I have to search some attribute for avoiding this.

Also have a look at the blockdiag library. Currently untested for me but it has been in my bookmarks for some time.

(Nov-13-2020, 10:18 AM)Gribouillis Wrote: [ -> ]Also have a look at the blockdiag library. Currently untested for me but it has been in my bookmarks for some time.

Yes I've already checked that library but when I tried it I was not able to do multiple connection between 2 nodes and set labels on the input/output pins.
For the overlapping of head/tail labels problem maybe I found a (dirty) solution. Since here is said that there is no control of that types of label, I decided to create an empy edge label with a number of space equal to len(headlabel)+len(taillabel)+5. It seems to work.