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List index out of range error while accessing 2 lists in python
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List index out of range error while accessing 2 lists in python
#1
I have 2 Lists in my code.
data list is having len = 11
new_list is having len = 23

I have to search if a string from data list exists in new_list.. I can see that my target_data gets filled with data,but when i go to print it i get an error..

here is my code:

        print len(new_list)
		print len(data)
		
		for i in range(len(new_list)):
			parts = (new_list[i].split('|'))
			#print parts
			if (int(parts[8]) >= 1 or int(parts[9])  >= 1 or int(parts[11])  >= 1 ):
				variable = parts[1]
				variable = variable.strip()
				variable = variable + "']"
				#print variable
				for d in data:
					if variable in d:
						target_data.append(d)	
						print "ok"
					else:
						NODATA = 1
			else:
				NODATA = 1
		print target_data
Error:
23 11 ok ok ok ok ok ok ok ok ok ok ok list index out of range
How do i take care of this list out of range error?
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#2
list indexes are 0-based, so the max index is len(some_list)-1. That said - don't use for i in range(len(new_list)) to iterate over list. Look at https://python-forum.io/Thread-Basic-Nev...n-sequence

In addition - you do some weird stuff like variable = variable + "']" Can you provide sample data for both lists and expected output?
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#3
(Sep-29-2020, 05:08 AM)buran Wrote: list indexes are 0-based, so the max index is len(some_list)-1. That said - don't use for i in range(len(new_list)) to iterate over list. Look at https://python-forum.io/Thread-Basic-Nev...n-sequence

In addition - you do some weird stuff like variable = variable + "']" Can you provide sample data for both lists and expected output?

data list contents
Output:
RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 315 10 Port 'clka' is not registered [Hierarchy: 'block_ram_top.blk_mem_inst_0'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 315 10 Port 'clka' is not registered [Hierarchy: 'block_ram_top.blk_mem_inst_1'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 317 10 Port 'ena' is not registered [Hierarchy: 'block_ram_top.latch'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 317 10 Port 'ena' is not registered [Hierarchy: 'block_ram_top.ff1'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 319 10 Port 'wen' is not registered [Hierarchy: 'block_ram_top']
new_list contents
Output:
| block_ram_top | (top) | 23 | 23 | 0 | 0 | 138 | 0 | 2 | 0 | 4 | | (block_ram_top) | (top) | 7 | 7 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | | blk_mem_inst_0 | blk_mem_gen_0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | (blk_mem_inst_0) | blk_mem_gen_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
variables that i extract in my code
Output:
inst_blk_mem_gen'] gnbram.gnativebmg.native_blk_mem_gen'] valid.cstr'] ramloop[0].ram.r'] prim_noinit.ram'] blk_mem_inst_1'] U0'] block_ram_top'] blk_mem_inst_0'] complex_multiplier_inst']
Expected target_data list: This should have all the data list items having the variable that i extract from the new_list items
Output:
RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 315 10 Port 'clka' is not registered [Hierarchy: 'block_ram_top.blk_mem_inst_0'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 315 10 Port 'clka' is not registered [Hierarchy: 'block_ram_top.blk_mem_inst_1'] RegInputOutput-ML Warning /sitework/soc/users/law/yeppy2/yeppy2chewy/yeppy2chewy_4ports/yeppy2/Spy_test_prj/mem/project_1/project_1.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd 319 10 Port 'wen' is not registered [Hierarchy: 'block_ram_top']
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